Hi Allan,
As the "node" has become smaller - the industry term for the smallest
dimension you can fabricate on a chip - the densities have of course
increased.
When you look at the history of mankind, at any one moment in time you
could point to a group of individuals or an individual who would represent
the artisans at the very leading edge of fabrication technology.
Early on, there was someone who got a rock that first time and banged it
into something a little pointier and over a two and half million years and
generation upon generation, there would have been someone who
represented the leading edge in honing these tools.
Fast forward to today and if you asked me, "Who is carrying that torch
today? Who represents the very leading edge in tool making?", then
arguably I might point you to the artisans in a Dutch company the
person in the street is unlikely to have ever heard of - ASML in
Veldhoven.
They make the world's most advanced machines that are used to
fabricate the world's most advanced chips. The leading edge has the node
down to 3nm. Now given visible blue light goes down to 450nm, these
guys are now honing the rock at dimensions below what the eye can
see even with a powerful optical microscope. It requires photolithography
at extreme ultra violet wavelengths - by definition hard to do
because that is the leading edge.
Here is an 18 minute video from CNBC from last year where you can see
them building these machines at ASML :-
https://youtu.be/iSVHp6CAyQ8
There is a packaging technology called System on Chip (SoC) that has
been around for decades which entails putting several silicon dies into
the one package.
Devices like these AMD parts use the latest iteration of that - what are
called chiplets - where multiple smaller dies are packaged together and
interconnected. As die sizes increase, yield goes down so the chiplets help
keep the die sizes in a reliable higher-yield sweet spot and they can pick
the ones that work and package them together.
Just like the system level PCI bus there is a new universal chiplet
interconnect express (UCIe) standard which was defined by an industry
consortium to assist with die-to-die connections.
There is a an industry presentation of "An Overview of Chiplet Technology
for the AMD EPYC" here :-
https://youtu.be/wqRAG_5KzBE
In chip design, unless it is something regular like memory, what we call
"interconnect" dominates. Interconnect are the traces that go between
transistors or sets of logic. Things like busses in a CPU design. The
transistors and logical components they form can look tiny compared to
the amount of interconnect between them.
The speed of light is disappointingly slow. Ideally, the chip would be
monolithic and small, all fabricated on one die so that the interconnect is
kept short and the propagation delays kept low. With Systems on Chip
and chiplets, there are longer interconnects between dies and hence
some communication paths become slower than ideal. Juggling these
around, ensuring there are large tightly coupled register sets and
cache memories, are some of the things you play with in computer
architecture.
A long way from Og, or whoever that first hominid was who banged
the first rocks together. But carrying the same legacy.
