Quote:
Originally Posted by gary
Hi Dennis,
It's pretty cool. 
I have attached a couple of snapshots I just took of a core memory board
I own which came out of an IBM 360/50 mainframe from the 1960's.
When it was new, it would have cost some eye-watering amount of money.
This has higher density than the core memory that was in the AGC
and the cores themselves are even too small to see naked eye.
Where you mentioned reading was destructive, that is right.
Three wires pass through each core. One to flip it to the '1' state,
another to flip it to the '0' state and a sense wire.
So to read a bit back, you would attempt to flip it to the '1' state whilst
monitoring the sense wire. If it was already in the '1' state then the
magnetic flux would barely change and the sense wire would detect
nothing. If it was in the '0' state and you just flipped it to '1', you would
detect the change in flux in the sense wire and then you would have to
restore it by flipping it back to '0' again.
It did have one enormous advantage over the DRAM sitting in your
PC right now in that if you cut the power it would retain its contents.
Remarkably the AGC firmware was woven into the core as a form of
read-only memory (ROM). |
Thanks Gary - but that begs the question, who assembles the wiring looms and multi-plane boards for the core memory boards in Argo Navis...
It was interesting to see the re-furb team playing around with the various input signal levels to obtain a clean core switching profile, noting that they were also concerned about the heating effects, so had to use short pulses.
I am now even more enthralled by and astonished with the Mercury, Gemini & Apollo program achievements.
Time to visit the museum again methinks.
Cheers
Dennis