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Old 02-08-2016, 06:46 PM
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wasyoungonce (Brendan)
Certified Village Idiot

wasyoungonce is offline
Join Date: Jul 2006
Location: Mexico city (Melb), Australia
Posts: 2,312
Absolutely Filip...

What needs to be done for each PCB design is not only a base level noise level but also a readout noise signature. I guess grim would be best to talk to on this. IMHO...wee need to separate the Power supplies to a different sub PCB and shield this. Then make the main PCB. Of course this philosophy needs to be measured...again back to grim and measuring signal noise. Ensure de-coupling caps are as close to the ICs as possible. Look at ceramic caps noise values...especially high value caps...they have an effect depending upon their dialectic.

About the only figure I saw was Grim stating he got down to ~ 4.7eV dark noise value, which is about base value for this sensor and indeed very good for any CMOS sensor. Again readout is an issue.

As said, separating and shielding the power would help a lot but...this needs quantification to which only grim can supply. This is what he mentioned in his original round PCB. He basically said...the noise floor was to high...and did not elaborate. Could be a language issue at play here.

But Luka and I both agree....separate the power from main PCB, shield it, would go a long way to improving the system. We both agree this is an iteration of design (cam 86 rectangle PCB) that will not end here. Oh .....there are other small ceramic capacitor noise values (from pizeo effect) that can be effected by dielectric used... a whole can of worms...

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